DSPIC33FJ32GP204 Operating Conditions

• 3.0V to 3.6V, -40°C to +150°C, DC to 20 MIPS

• 3.0V to 3.6V, -40°C to +125°C, DC to 40 MIPS

DSPIC33FJ32GP204 Core: 16-Bit dsPIC33F CPU

• Code-efficient (C and Assembly) architecture

• Two 40-bit wide accumulators

• Single-cycle (MAC/MPY) with dual data fetch

• Single-cycle, mixed-sign MUL plus hardware divide

DSPIC33FJ32GP204 Clock Management

• ±2% internal oscillator

• Programmable PLLs and oscillator clock sources

• Fail-Safe Clock Monitor (FSCM)

• Independent Watchdog Timer (WDT)

• Fast wake-up and start-up

DSPIC33FJ32GP204 Power Management

• Low-power management modes (Sleep, Idle, Doze)

• Integrated Power-on Reset and Brown-out Reset

• 1.35 mA/MHz dynamic current (typical)

• 55 μA IPD current (typical)

Advanced Analog Features

• ADC module:

- Configurable as 10-bit, 1.1 Msps with four S/H (Sample-and-Hold) or 12-bit, 500 ksps with one S/H

- Ten analog inputs on 28-pin devices and up to 13 analog inputs on 44-pin devices

• Flexible and independent ADC trigger sources

Timers/Output Compare/Input Capture

• Three 16-bit timers/counters; can pair up two to make one 32-bit

• Two OC modules, configurable as timers/counters

• Four IC modules

• Peripheral Pin Select (PPS) to allow function remap

Communication Interfaces

• One UART module (10 Mbps)

- With support for LIN/J2602 protocols and IrDA ®

• One 4-wire SPI module (15 Mbps)

• One I 2 C™ module (up to 1 Mbaud) with SMBus support

• PPS to allow function remap

Input/Output

• Sink/Source up to 10 mA (pin-specific) for standard V OH /V OL , up to 16 mA (pin-specific) for non-standard V OH 1

• 5V tolerant pins

• Selectable open-drain, pull-ups, and pull-downs

• Up to 5 mA overvoltage clamp current

• External interrupts on all I/O pins

Qualification and Class B Support

• AEC-Q100 REVG (Grade 1 -40°C to +125°C)

• AEC-Q100 REVG (Grade 0 -40°C to +150°C)

• Class B Safety Library, IEC 60730

Debugger Development Support

• In-circuit and in-application programming

• Two program and two complex data breakpoints

• IEEE 1149.2-compatible (JTAG) boundary scan

• Trace and run-time watch

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