GENESYS/创惟科技 GL850G-OHY60 QFN-28 USB 2.0集线器控制器

GL850G-OHY60 FEATURES

● Compliant to USB Specification Revision 2.0

GL850G-OHY60 Support 4/3/2 downstream ports by I/O pin configuration

Upstream port supports both high-speed (HS) and full-speed (FS) traffic

Downstream ports support HS, FS, and low-speed (LS) traffic

1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload)

Backward compatible to USB specification Revision 1.1

● On-chip 8-bit micro-processor

RISC-like architecture

USB optimized instruction set

Performance: 6 MIPS @ 12MHz

With 64-byte RAM and 2K mask ROM

Support customized PID, VID by reading external EEPROM

Support downstream port configuration by reading external EEPROM

● Single Transaction Translator (STT)

Single TT shares the same TT control logics for all downstream port devices. This is the most cost effective solution for TT. Multiple TT provides individual TT control logics for each downstream port. This is a performance better choice for USB 2.0 hub. Please refer to GL852G datasheet for more detailed information.

● Integrate USB 2.0 transceiver

● Built-in upstream 1.5KΩ pull-up and downstream 15KΩ pull-down

● Embed serial resister for USB signals

● Conform to bus power requirements

● Automatic switching between self-powered and bus-powered modes

● Support compound-device (non-removable in downstream ports) by I/O pin configuration

● Configurable non-removable device support

● Built-in PLL supports external 12 MHz crystal / Oscillator clock input

● Built-in 5V to 3.3V regulator

● Low power consumption

● Improve output drivers with slew-rate control for EMI reduction

● Internal power-fail detection for ESD recovery

● Each downstream port supports two-color status indicator, with automatic and manual modes compliant to USB specification Revision 2.0 (Not available for SSOP 28 package)

● Support both individual and gang modes of power management and over-current detection for downstream ports (Individual mode is not supported by SSOP 28 package)

● Power enable pin supports both low/high-enabled power switches. (Power switch is not supported by GL850G-22 SSOP28 package)

● Optional 27/48 MHz Oscillator clock input (Not available for QFN28 / SSOP28 package)

● Number of Downstream port can be configured by GPIO without external EEPROM

GL850G-OHY60规格书（部分）

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