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逻辑 SN74HC166N 计数器移位寄存器 详资料

逻辑 SN74HC166N 计数器移位寄存器 详资料
逻辑 SN74HC166N 计数器移位寄存器 详资料
  • 型号/规格:

    SN74HC166N

  • 品牌/商标:

    TI(德州仪器)

  • 计数顺序:

    Serial/Parallel to Serial

  • 电路数量:

    1

  • 位数:

    8

  • 输入线路数量:

    5 / 3

  • 传播延迟时间:

    150 ns, 30 ns, 26 ns

  • 电源电压-:

    6 V

  • 工作温度:

    - 40 C

  • 工作温度:

    + 85 C

  • 输出线路数量:

    3

  • PDF资料:

    点击下载PDF

VIP会员 第 13
  • 企业名:深圳市勤思达科技有限公司

    类型:贸易/代理/分销

    电话: 0755-83264115
    0755-82710921

    手机:15889758566
    13714022780

    联系人:朱亮成/18948336722

    QQ: QQ:2881239445QQ:2881243225

    微信:

    邮箱:1282971461@qq.com

    地址:广东深圳深圳市福田区华强北赛格科技园四栋中12楼A4座—2L

产品分类
商品信息

型号:SN74HC166N 
品牌:TI
厂家:Texas Instruments
描述: 8-Bit Parallel-Load Shift Registers 16-PDIP -40 to 85 
类别:集成电路 (IC)
家庭:逻辑 - 移位寄存器
系列:74HC
逻辑类型:移位寄存器
输出类型:标准
元件数:1
每个元件的位元数:8
功能:并行或串行至串行
电源电压:2 V ~ 6 V
工作温度:-40°C ~ 85°C
安装类型:通孔
封装/外壳:16-DIP(0.300",7.62mm)
供应商设备封装:16-PDIP
包装:管件
其它名称:296-8255-5

标准包装:25

SN74HC166N SN74HC166N SN74HC166N


 Wide Operating Voltage Range of 2 V to 6 V

 Outputs Can Drive Up To 10 LSTTL Loads

 Low Power Consumption, 80-μA Max ICC

 Typical tpd = 13 ns

 ±4-mA Output Drive at 5 V

 Low Input Current of 1 μA Max

 Synchronous Load

 Direct Overriding Clear

 Parallel-to-Serial Conversion

description/ordering information (continued)

These parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an overriding

clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high,

SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock

(CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on

the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the

low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a

clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low

enables the other clock input. This allows the system clock to be free running, and the register can be stopped

on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.

CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.


联系方式

企业名:深圳市勤思达科技有限公司

类型:贸易/代理/分销

电话: 0755-83264115
0755-82710921

手机:15889758566
13714022780

联系人:朱亮成/18948336722

QQ: QQ:2881239445QQ:2881243225

微信:

邮箱:1282971461@qq.com

地址:广东深圳深圳市福田区华强北赛格科技园四栋中12楼A4座—2L

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