High-Performance Static CMOS Technology
Includes the T320C2xLP Core CPU
TMS320F206 is a Member of the
TMS320C20x Generation, Which Also
Includes the TMS320C203, and
TMS320C209 Devices
Instruction-Cycle Time 50 ns @ 5 V
Source Code Compatible With TMS320C25
Upwardly Code-Compatible With
TMS320C5x Devices
Three External Interrupts
TMS320F206 Integrated Memory:
– 544
×
16 Words of On-Chip Dual-Access
Data RAM
– 32K
×
16 Words of On-Chip Flash
Memory (EEPROM)
– 4K
×
16 Words of On-Chip Single-Access
Program/ Data RAM
224K
×
16-Bit Maximum Addressable
External Memory Space
– 64K Program
– 64K Data
– 64K Input/Output (I/O)
– 32K Global
32-Bit ALU / Accumulator
16
×
16-Bit Multiplier With a 32-Bit Product
Block Moves from Data and Program
Space
TMS320F206 Peripherals:
– On-Chip 16-Bit Timer
– On-Chip Software-Programmable
Wait-State (0 to 7) Generator
– On-Chip Oscillator
– On-Chip Phase-Locked Loop (PLL)
– Six General-Purpose I/O Pins
– Full-Duplex Asynchronous Serial Port
(UART)
– Enhanced Synchronous Serial Port
(ESSP) With Four-Level-Deep FIFOs
Input Clock Options
– Options – Multiply-by-One, -Two, or -Four
and Divide-by-Two
Support of Hardware Wait States
Power Down IDLE Mode
IEEE 1149.1
†
-Compatible Scan-Based
Emulation
100-Pin Thin Quad Flat Package (TQFP)
(PZ Suffix)
description
The TMS320F206 Texas Instruments (TI™) digital signal processor (DSP) is fabricated with static CMOS
integrated-circuit technology, and the architectural design is based upon that of the TMS320C20x series,
optimized for low-power operation. The combination of advanced Harvard architecture, on-chip peripherals,
on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of
the ’F206.
The ’F206 offers these advantages:
32K
16 words on-chip flash EEPROM reduces system cost and facilitates prototyping
Enhanced TMS320 architectural design for increased performance and versatility
Advanced integrated-circuit processing technology for increased performance
’F206 devices are pin- and code-compatible with ’C203 devices.
Source code for the ’F206 DSP is software-compatible with the ’C1x and ’C2x DSPs and is upwardly
compatible with fifth-generation DSPs (’C5x)
New static-design techniques for minimizing power consumption and increasing radiation tolerance
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