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Hi3516E V100 Professional HD IP Camera SoC Brief Data Sheet

Issue 01 (2017-06-07)

HiSilicon Proprietary and Confidential

Copyright © HiSilicon Technologies Co., Ltd.

1

Key Specifications

Processor Core

ARM926@800 MHz with 32 KB I-cache and 32 KB D-cache

Video Encoding

 H.264 BP/MP/HP

 H.265 Main Profile

 MJPEG/JPEG baseline

Video Encoding Performance

 Maximum resolution of 1536 x 1536 for H.264/H.265

encoding, and maximum width of 2048

 Real-time multi-stream H.264/H.265 encoding capabilities

− 1920 x 1080@20 fps+720 x 576@20 fps

 JPEG snapshot at 2 megapixels@5 fps

 CBR, VBR, FIXQP, AVBR, and QPMAP modes

 Maximum 30 Mbit/s output bit rate

 Encoding of eight ROIs

Intelligent Video Analysis

Integrated IVE, supporting various intelligent analysis

applications such as motion detection, perimeter defense, and

video diagnosis

Video and Graphics Processing

 3DNR, image enhancement, and DCI

 Anti-flicker for output videos and graphics

 1/15x to 16x video and graphic scaling

 Overlaying of video and graphics

 Picture rotation by 90°, 180° or 270°

 Picture mirroring and flipping

 OSD overlaying of eight regions before encoding

ISP

 3A (AE, AF, and AWB) function. The third-party 3A

algorithms are supported.

 FPN removal and DPC

 LSC, LDC, and purple edge correction

 Direction-adaptive demosaic

 Gamma correction, DCI, and color management and

enhancement

 Adaptive region de-fog

 Multi-level NR (BayerNR and 3DNR) and sharpening

enhancement

 Local tone mapping

 Sensor built-in WDR

 DIS

 ISP tuning tools for the PC

Audio Encoding/Decoding

 Voice encoding/decoding complying with multiple

protocols by using software

 Compliance with the G.711, G.726, and ADPCM

protocols

 Audio 3A functions (AEC, ANR, and AGC)

Security Engine

 Various encryption and decryption algorithms

implemented by using hardware, including AES, DES,

3DES, and RSA

 HASH (SHA1/SHA256/HMAC_SHA/HMAC_SHA256)

algorithms implemented by using hardware

 Integrated 512-bit one-time program only and random

number generator

Video Interfaces

 VI interfaces

− 8-/10-/12-/14-bit RGB Bayer DC timing VI

− BT.601, BT.656, and BT.1120 VI interfaces

− MIPI, LVDS/sub-LVDS, and HiSPi

− Compatibility with mainstream HD CMOS sensors

provided by Sony, ON, OmniVision, and Panasonic

− Compatibility with the electrical specifications of

parallel and differential interfaces of various sensors

− Programmable sensor clock output

− Maximum input resolution of 2048 x 2048, up to 250

megapixels/s

 VO interfaces

− One BT.656 VO interface

− 6-bit RGB565 serial LCD output

Audio Interfaces

 Integrated audio CODEC supporting 16-bit audio inputs

and outputs

 Mono-channel differential MIC inputs for reducing the

background noises

 Single-ended dual-channel input

 I2S interface for connecting to the external audio CODEC

Peripheral Interfaces

 POR

 One integrated high-precision RTC

 Integrated 3-channel LSADC

 Three UART interfaces (including one 4-wire interface)

 IR, I2C, SPI, and GPIO interfaces

 Four PWM interfaces

 Two SDIO 2.0 interfaces, supporting the 3.3 V level and

1.8 V level

 One USB 2.0 host/device port

 RMII in 10/100 Mbit/s full-duplex or half-duplex mode,

TSO network acceleration, and PHY clock output

External Memory Interfaces

 SDRAM interface

− Embedded 512 MB DDR

 SPI NOR flash interface

− 1-/2-/4-wire mode

− Maximum capacity of 32 MB

 SPI NAND flash interface with maximum 4 Gbits

capacity

 SD card interface supporting the maximum capacity of 2

TB

 eMMC 4.5 interface with 4-bit data width

Boot

 Booting from the SPI NOR flash, SPI NAND flash, or

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