MPC8309CVMAGDCA

微处理器 - MPU E300 MP EXT TMP

Overview

The MPC8309CVMAGDCA incorporates the e300c3 (MPC603e-based) core built on Power Architecture® technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and a 16/32-bit DDR2 memory controller with 8-bit ECC.

Features MPC8309CVMAGDCA

The major features of the device are as follows:

• e300c3 Power Architecture processor core

— Enhanced version of the MPC603e core

— High-performance, superscalar processor core with a four-stage pipeline and low interrupt latency times

— Floating-point, dual integer units, load/store, system register, and branch processing units

— 16-Kbyte instruction cache and 16-Kbyte data cache with lockable capabilities

— Dynamic power management

— Enhanced hardware program debug features

— Software-compatible with Freescale processor families implementing Power Architecture technology

— Separate PLL that is clocked by the system bus clock

— Performance monitor

• QUICC Engine block MPC8309CVMAGDCA

— 32-bit RISC controller for flexible support of the communications peripherals with the following features:

– One clock per instruction

– Separate PLL for operating frequency that is independent of system’s bus and e300 core frequency for power and performance optimization

– 32-bit instruction object code

– Executes code from internal IRAM

– 32-bit arithmetic logic unit (ALU) data path

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