AT91SAM9263B-CU-100

微处理器 - MPU 32-bit MCU

Description AT91SAM9263B-CU-100

The AT91SAM9263 32-bit microcontroller, based on the ARM926EJ-S processor, is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It also features two independent external memory buses, EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses prevent bottlenecks, thus guaranteeing maximum performance.

Features AT91SAM9263B-CU-100

• Incorporates the ARM926EJ-S™ ARM® Thumb® Processor

– DSP Instruction Extensions, Jazelle® Technology for Java® Acceleration

– 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer

– 220 MIPS at 200 MHz

– Memory Management Unit

– EmbeddedICE™, Debug Communication Channel Support

– Mid-level Implementation Embedded Trace Macrocell™

• Bus Matrix AT91SAM9263B-CU-100

– Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth

– Boot Mode Select Option, Remap Command

• Embedded Memories

– One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed

– One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus Matrix Speed

– One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed

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