SN75LVDS82	SN75LVDS83A	SN75LVDS83B
Number of Parallel Outputs	28
Number of Parallel Inputs		28	28
Data Throughput(MB/s)	227.5
Serial Data Receiver Channels	4
Serial Data Transmitter Channels		4	4
Type of Line Circuit	LVDS	LVDS	LVDS
Driver (RL)(Ohms)		100	100
Receiver (Vth)(mV)	100
Supply Voltage(s)(V)	3.3	3.3	3.3
Driver tpd(ns)		14.2	14.2
Receiver tpd(ns)	8.7
ICC(mA)	125	110	110
PLL Frequency(MHz)	31 - 68	10 - 100	10 - 135
Footprint	DS90C582	DS90C385A	DS90C385A
Operating Temperature Range(°C)	0 to 70	-10 to 70	-10 to 70
Pin/Package	56TSSOP	56BGA MICROSTAR JUNIOR, 56TSSOP	56BGA MICROSTAR JUNIOR, 56TSSOP

特性

• 4:28 Data Channel Expansion at up to 238 Mbytes/s Throughput
• Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI
• Four Data Channels and Clock Low-Voltage Differential Channels In and 28 Data and Clock Low-Voltage TTL Channels Out
• Operates From a Single 3.3-V Supply With 250 mW (Typ)
• 5-V Tolerant SHTDN Input
• Falling Clock-Edge-Triggered Outputs
• Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
• Consumes Less Than 1 mW When Disabled
• Wide Phase-Lock Input Frequency Range. . . 31 MHz to 68 MHz
• No External Components Required for PLL
• Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
• Improved Replacement for the National™ DS90C582

FlatLink is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

说明

The SN75LVDS82 FlatLink™ receiver contains four serial-in, 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit.

These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL) synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 or SN75LVDS85 for 21-bit transfers.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×) the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate.

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