| 系列 ： |
XC9500XL |
| 可编程类型 ： |
系统内可编程（少 10,000 次编程/擦除循环） |
| 延迟时间 tpd(1) ： |
10.0ns |
| 电压电源 - 内部 ： |
3 V ~ 3.6 V |
| 逻辑元件/逻辑块数目 ： |
4 |
| 宏单元数 ： |
72 |
| 门数 ： |
1600 |
| 输入/输出数 ： |
34 |
| 工作温度 ： |
0°C ~ 70°C |
| 描述 ： |
IC CPLD 72MCRCELL 10NS 44VQFP |
| 封装/外壳 ： |
44-TQFP |
| 包装 ： |
托盘 |
Features
• 5 ns pin-to-pin logic delays
• System frequency up to 178 MHz
• 72 macrocells with 1,600 usable gates
• Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
- Pb-free available for all packages
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC9572 device in the
44-pin PLCC package and the 100-pin TQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
