ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. 32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM DECEMBER 2013 IS42S83200G IS42S16160G 8M x 8 x 4 Banks 4M x16x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball BGA 54-ball BGA Parameter 32M x 8 16M x 16 Configuration 8M x 8 x 4 banks 4M x 16 x 4 banks Refresh Count Com./Ind. A1 A2 8K/64ms 8K/64ms 8K/32ms 8K/64ms 8K/64ms 8K/32ms Row Addresses A0-A12 A0-A12 Column Addresses A0-A9 A0-A8 Bank Address Pins BA0, BA1 BA0, BA1 Auto Precharge Pins A10/AP A10/AP ADDRESS TABLE KEY TIMING PARAMETERS Parameter -5 -6 -7 Unit Clk Cycle Time CAS Latency = 3 5 6 7 ns CAS Latency = 2 10 10 7.5 ns Clk Frequency CAS Latency = 3 200 166 143 Mhz CAS Latency = 2 100 100 133 Mhz Access Time from Clock CAS Latency = 3 5 5.4 5.4 ns CAS Latency = 2 5 

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