XILINX复杂可编程逻辑器件XC95288XL-10PQG208I规格

制造商
Xilinx Inc.
制造商零件编号
XC95288XL-10PQG208I
描述 IC CPLD 288MC 10NS 208QFP
产品属性
类别 集成电路（IC）
嵌入式 - CPLD（复杂可编程逻辑器件）
制造商 Xilinx Inc.
系列 XC9500XL
可编程类型 系统内可编程（少 10，000 次编程/擦除循环）
延迟时间 tpd（1）值 10.0ns
电源电压 - 内部 3 V ~ 3.6 V
逻辑元件/块数 16
宏单元数 288
栅极数 6400
I/O 数 168
工作温度 -40°C ~ 85°C（TA）
封装/外壳 208-BFQFP
Features
• 6 ns pin-to-pin logic delays
• System frequency up to 208 MHz
• 288 macrocells with 6,400 usable gates
• Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 256-pin BGA (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
- 280-pin CSP (192 user I/O pins)
- Pb-free available for all packages
• Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
• Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
• Fast concurrent programming
• Slew rate control on individual outputs
• Enhanced data security features
• Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
• Pin-compatible with 5V-core XC95288 device in the
208-pin HQFP package
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XC95288XL is a 3.3V CPLD targeted for high-performance,
low-voltage applications in leading-edge communications
and computing systems. It is comprised of 16
54V18 Function Blocks, providing 6,400 usable gates with
propagation delays of 6 ns. See Figure 2 for architecture
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depending
on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addition,
unused product-terms and macrocells are automatically
deactivated by the software to further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f
where:
MCHS = # macrocells in high-speed configuration
PTHS = average number of high-speed product terms
per macrocell
MCLP = # macrocells in low power configuration
PTLP = average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be verified
during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx

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