供应MD82C50A-5/B 丝印MD82C50A-5/B    90片   实物拍照进口原装！

供应MD82C50A-5/B 丝印MD82C50A-5/B实物拍照进口原装！

供应MD82C50A-5/B 丝印MD82C50A-5/B    90个实物拍照进口原装！

供应MD82C50A-5/B 丝印MD82C50A-5/B实物拍照进口原装！

Features???????????????Single Chip UART/BRGDC to 625K Baud (DC to 10MHz Clock)Crystal or External Clock InputOn Chip Baud Rate Generator 1 to 65535 DivisorGenerates 16X ClockPrioritized Interrupt ModeFully TTL/CMOS CompatibleMicroprocessor Bus Oriented Interface80C86/80C88 CompatibleScaled SAJI IV CMOS ProcessLow Power - 1mA/MHz TypicalModem InterfaceLine Break Generation and DetectionLoopback and Echo ModesDoubled Buffered Transmitter and ReceiverSingle 5V SupplyOrdering InformationPACKAGEPDIPPLCCCERDIPTEMPERATURERANGE (oC)0 to +70-40 to +850 to +70-40 to +850 to +70-40 to +85-55 to +125625K BAUDCP82C50A-5IP82C50A-5CS82C50A-5IS82C50A-5CD82C50A-5ID82C50A-5MD82C50A-5/BPKG.NO.E40.6E40.6N44.65N44.65F40.6F40.6F40.6

DescriptionThe 82C50A Asynchronous Communication Element (ACE)is a high performance programmable Universal Asynchro-nous Receiver/Transmitter (UART) and Baud Rate Genera-tor (BRG) on a single chip. Using Intersil’s advanced ScaledSAJI IV CMOS Process, the ACE will support data ratesfrom DC to 625K baud (0-10MHz clock).The ACE’s receiver circuitry converts start, data, stop, andparity bits into a parallel data word. The transmitter circuitryconverts a parallel data word into serial form and appendsthe start, parity, and stop bits. The word length is program-mable to 5, 6, 7, or 8 data bits. Stop bit selection provides achoice of 1,1.5, or 2 stop bits.The Baud Rate Generator divides the clock by a divisorprogrammable from 1 to 216-1 to provide standard RS-232Cbaud rates when using any one of three industry standardbaud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz).A programmable buffered clock output (BAUDOUT) provideseither a buffered oscillator or 16X (16 times the data rate)baud rate clock for general purpose system use.To meet the system requirements of a CPU interfacing to anasynchronous channel, the modem control signals RTS,CTS, DSR, DTR, RI, DCD are provided. Inputs and outputshave been designed with full TTL/CMOS compatibility inorder to facilitate mixed TTL/NMOS/CMOS system design

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