JS28F128P30B85
INTEL
TSSOP
08+
企业名:深圳市尚想信息技术有限公司
类型:贸易/代理/分销
电话:
0755-83948880
0755-8398880
手机:15323892334
18182115682
联系人:姚小姐/邓小姐
微信:
邮箱:assistant@sunshineic.com
地址:广东深圳福田区振兴路上步工业区405栋6楼603室
The Latency Count bits, LC[2:0], tell the device how many clock cycles must elapse from the rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the first data word is to be driven onto DQ[15:0]. The input clock frequency is used to determine this value. Figure 28 shows the data output latency for the different settings of LC[2:0]. Synchronous burst with a Latency Count setting of Code 4 will result in zero WAIT state; however, a Latency Count setting of Code 5 will cause 1 WAIT state (Code 6 will cause 2 WAIT states, and Code 7 will cause 3 WAIT states) after every four words, regardless of whether a 16-word boundary is crossed. If RCR[9] (Data Hold) bit is set (data hold of two clocks) this WAIT condition will not occur because enough clocks elapse during each burst cycle to eliminate subsequent WAIT states.
企业名:深圳市尚想信息技术有限公司
类型:贸易/代理/分销
电话:
0755-83948880
0755-8398880
手机:15323892334
18182115682
联系人:姚小姐/邓小姐
微信:
邮箱:assistant@sunshineic.com
地址:广东深圳福田区振兴路上步工业区405栋6楼603室