FEATUR*
· Complies with JEDEC standard no. 8-1A
· *D protection:
HBM EIA/J*D22-A114-A exceeds 2000 V
MM EIA/J*D22-A115-A exceeds 200 V.
· Specified from -40 to +85 °C and -40 to +125 °C.
D*CRIPTION
The 74HC/H*08 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A. The 74HC/H*08 provide the 2-input
AND function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in mW).
PD = CPD ´ VCC
2 ´ fi ´ N + S(CL ´ VCC
2 ´ fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
S(CL ´ VCC
2 ´ fo) = sum of the outputs.
2. For 74HC08: the condition is VI = GND to VCC.
For 74H*08: the condition is VI = GND to VCC - 1.5 V.
FUN*ION TABLE
Note
1. H = HIGH voltage level;
L = LOW voltage level.
SY*OL PARAMETER CONDITIONS
TYPICAL
UNIT
74HC08 74H*08
tPHL/tPLH propagation delay nA, nB to nY CL = 15 pF; VCC = 5 V 7 11 ns
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per gate notes 1 and 2 10 20 pF
INPUT OUTPUT
nA nB nY
L L L
L H L
H L L
H H H

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