LFE3-17EA-6FN484C

FPGA - 现场可编程门阵列 17.3K LUTs 222 I/O 1.2V -6 Speed

Features LFE3-17EA-6FN484C

 Higher Logic Density for Increased System Integration

• 17K to 149K LUTs

• 116 to 586 I/Os

 Embedded SERDES

• 150 Mbps to 3.2 Gbps for Generic 8b10b, 10-bit

SERDES, and 8-bit SERDES modes

• Data Rates 230 Mbps to 3.2 Gbps per channel for all other protocols

• Up to 16 channels per device: PCI Express,

SONET/SDH, Ethernet (1GbE, SGMII, XAUI),

CPRI, SMPTE 3G and Serial RapidIO

 sysDSP™ LFE3-17EA-6FN484C

• Fully cascadable slice architecture

• 12 to 160 slices for high performance multiply and accumulate

• Powerful 54-bit ALU operations

• Time Division Multiplexing MAC Sharing

• Rounding and truncation

• Each slice supports

— Half 36x36, two 18x18 or four 9x9 multipliers

— Advanced 18x36 MAC and 18x18 MultiplyMultiply-Accumulate (MMAC) operations

Introduction LFE3-17EA-6FN484C

The LatticeECP3™ (EConomy Plus Third generation) family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES and high speed source synchronous interfaces in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 65 nm technology making the devices suitable for high-volume, high-speed, low-cost applications.

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