LCMXO2-1200HC-4TG100C

FPGA - 现场可编程门阵列 1280 LUTs 80 I/O 3.3V -4 SPD

Architecture Overview LCMXO2-1200HC-4TG100C

The MachXO2 family architecture contains an array of logic blocks surrounded by Programmable I/O (PIO). The larger logic density devices in this family have sysCLOCK™ PLLs and blocks of sysMEM Embedded Block RAM (EBRs). Figure 2-1 and Figure 2-2 show the block diagrams of the various family members.

Introduction LCMXO2-1200HC-4TG100C

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2 C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.

Features LCMXO2-1200HC-4TG100C

 Flexible Logic Architecture

• Six devices with 256 to 6864 LUT4s and 18 to 334 I/Os

 Ultra Low Power Devices

• Advanced 65 nm low power process

• As low as 22 μW standby power

• Programmable low swing differential I/Os

• Stand-by mode and other power saving options

 Embedded and Distributed Memory

• Up to 240 kbits sysMEM™ Embedded Block RAM

• Up to 54 kbits Distributed RAM

• Dedicated FIFO control logic

 On-Chip User Flash Memory

• Up to 256 kbits of User Flash Memory

• 100,000 write cycles

• Accessible through WISHBONE, SPI, I2C and JTAG interfaces

• Can be used as soft processor PROM or as Flash memory

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