1 General Description
The EM78P301N is an 8-bit microprocessor designed and developed with low-power and high-speed
CMOS technology. The device has an on-chip 1K×13-bit Electrical One Time Programmable Read Only
Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s OTP memory code. Three
Code option bits are also available to meet user’s requirements.
With enhanced OTP-ROM features, the EM78P301N provides a convenient way of developing and verifying
user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates,
using development and programming tools. User can avail of the ELAN Writer to easily program his
development code.

 

2 Features
CPU configuration
• 1K×13 bits on-chip ROM
• 80×8 bits on-chip registers (SRAM)
• 8-level stacks for subroutine nesting
• Less than 1.5 mA at 5V/4 MHz
• Typically 15 μA, at 3V/32kHz
• Typically 2 μA, during sleep mode
I/O port configuration
• 3 bidirectional I/O ports: P5, P6, P7
• 12 I/O pins
• Wake-up port : P5
• 8 programmable pull-down I/O pins (P50~P57)
• 10 programmable pull-high I/O pins (P50~P57,
P60, P67)
• 2 programmable open-drain I/O pins (P60, P67)
• 8 programmable high-sink current I/O pins
(P50~P57, P60, P67)
• External interrupt : P60
Operating voltage range:
• 2.1V~5.5V at 0°C~70°C (commercial)
• 2.3V~5.5V at -40°C~85°C (industrial)
Operating frequency range (base on 2 clocks):
• Crystal mode: DC ~ 16 MHz, 4.5V;
DC ~ 8 MHz, 3V; DC ~ 4 MHz, 2.1V
• ERC mode: DC ~ 2 MHz, 2.1V;
• IRC mode
Oscillation mode: 16 MHz, 4 MHz, 1 MHz, 8 MHz

 

Fast set-up time requires only 0.8ms (VDD: 5V
Crystal: 4 MHz, C1/C2: 15pF) in XT mode and
10μs in IRC mode (VDD: 5V, IRC: 4 MHz)
Peripheral configuration
• 8-bit real time clock/counter (TCC) with
selective signal sources, trigger edges, and
overflow interrupt
• 4 programmable Level Voltage Detector
(LVD) : 4.5V, 4.0V, 3.3V, 2.2V
• Power-on reset and three programmable level
voltage reset
POR: 1.8V (Default), LVR: 4.0, 3.5, 2.7V
• 8-bit multi-channel Analog-to-Digital Converter
with 12-bit resolution in Vref (2/3/4v) mode
• Two Pulse Width Modulation (PWM) with 8-bit
resolution
Nine available interrupts
• TCC overflow interrupt
• Input-port status changed interrupt (wake up
from sleep mode)
• External interrupt
• ADC completion interrupt
• Low voltage detect (LVD) interrupt
• PWM 1~2 period match interrupt
• PWM 1~2 duty match interrupt
Special Features
• Programmable free running Watchdog Timer
(4.5 ms : 18 ms)
• Power saving Sleep mode
• Power-on voltage detector available
• High EFT immunity (better performance at
4 MHz or below)
Package Type:
• 10-pin MSOP 118mil : EM78P301NMS10J
• 14-pin DIP 300mil : EM78P301ND14J
• 14-pin SOP 150mil : EM78P301NSO14J
Note: These are Green products that do not contain
hazardous substances.

 

6 Functional Description
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as an indirect address pointer.
Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM
Select Register (R4).
6.1.2 R1 (Time Clock/Counter)
Incremented by an external signal edge which is defined by the TE bit (CONT-5)
through the TCC pin, or by the instruction cycle clock.
Writable and readable as any other registers.
The TCC prescaler counter is assigned to TCC
The contents of the CONT register is cleared whenever –
• a value is written to the TCC register
• a value is written to the TCC prescaler bits (Bits 3, 2, 1, 0 of the CONT register)
• there’s power-on reset, /RESET, or WDT time out reset

 

R2 and hardware stacks are 10-bit wide. The structure is depicted in the table
under Section 6.1.3.1 Data Memory Configuration.
The configuration structure generates 1K×13 bits on-chip ROM addresses to the
relative programming instruction codes. One program page is 1024 words long.
The contents of R2 are all set to "0"s when a reset condition occurs.
"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus,
"JMP" allows the PC to jump to any location within a page.
"CALL" instruction loads the lower 10 bits of the PC, and PC 1 are pushed onto the
stack. Thus, the subroutine entry address can be located anywhere within a page.
"RET" ("RETL k", "RETI") instruction loads the program counter with the contents
of the top of the stack.
"ADD R2, A" allows a relative address to be added to the current PC, and the ninth
and above bits of the PC will increase progressively.
"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of
the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged.
Any instruction (except “ADD R2, A”) that is written to R2 (e.g., "MOV R2, A", "BC
R2, 6", etc.) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain
unchanged.
All instructions are single instruction cycle (fclk/2) except “LCALL” and “LJMP”
instructions. The “LCALL” and “LJMP” instructions need two instruction cycles.

 

 

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