H5AN4G6NBJR-UHI  原装全新DDR4 

 

 

1.  VDD=VDDQ=1.2V +/- 0.06V

2. Fully differential clock inputs (CK, CK) operation

3. Differential Data Strobe (DQS, DQS)

4.  On chip DLL align DQ, DQS and DQS transition with CK transition

5. DM masks write data-in at the both rising and falling  edges of the data strobe

6. All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

7.  Programmable CAS latency 9, 11, 12, 13, 14, 15, 16,17, 18, 19 and 20

8.  Programmable additive latency 0, CL-1, and CL-2 supported (x4/x8 only)

9. Programmable CAS Write latency (CWL) = 9, 10, 11,12, 14, 16, 18

10. Programmable burst length 4/8 with both nibble sequential and interleave mode

11. BL switch on the fly

12.  16banks

13. Average Refresh Cycle (Tcase of 0 oC~ 95 oC)

 - 7.8 μs at 0oC ~ 85 oC

 - 3.9 μs at 85oC ~ 95 oC

16.  Operating Temperture Range

 - Commercial Temperature (0 oC~ 95 oC)

 - Industrial Temperature (-40oC~ 95 oC)

19. ? JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16)

20. ? Driver strength selected by MRS

21. ? Dynamic On Die Termination supported

 

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