32-BITCMOSMICROCONTROLLER

FEATUR*
Architecture
?  Integrated system for hand-held devices and
general embedded applications.
?  16/32-Bit RISC architecture and powerful
instruction set with ARM920T CPU core.
?  Enhanced ARM architecture MMU to support
WinCE, EPOC 32 and Linux.
?  Instruction cache, data cache, write buffer and
Physical address TAG RAM to reduce the effect of
main memory bandwidth and latency on
performance.
?  ARM920T CPU core supports the ARM debug
architecture.
?  Internal Advanced Microcontroller Bus Architecture
(A*A) (A*A2.0, AHB/APB).

NAND Flash Boot Loader
?  Supports booting from NAND flash memory.
?  4KB internal buffer for booting.
?  Supports storage memory for NAND flash memory
after booting.
?  Supports Advanced NAND flash
Cache Memory
?  64-way set-*ociative cache with I-Cache (16KB)
and D-Cache (16KB).
?  8words length per line with one valid bit and two
dirty bits per line.
?  Pseudo random or round robin replacement
algorithm.
?  Write-through or write-back cache operation to
update the main memory.
?  The write buffer can hold 16 words of data and four
addresses.